The present disclosure relates generally to semiconductor devices, and more particularly to fin field effect transistors (FinFETs) and their methods of fabrication.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
A trend in the development of semiconductor manufacturing technologies has been to increase the density of devices per chip, and hence decrease the size of active structures as well as the distances between such structures. An increase in device density may advantageously affect device performance such as circuit speed, and may allow also for increasingly complex designs and functionality. However, the decrease in size and the attendant increase in density may also generate undesirable effects, including unwanted short circuits between adjacent conductive elements.
In various approaches to scaling FinFETs to increasingly greater device densities, an individual fin may be cut or severed to define distinct regions among remaining portions of the fin that may be used to form independent devices. Such a process typically involves etching unwanted portions of a fin to form a cut region, and backfilling the cut region with a dielectric material to isolate the remaining active regions of the fin on either side of the cut region. The resulting isolation structure may be referred to as a single diffusion break, where a lateral width in the current direction or gate length direction of the dielectric material between the two active regions is less than or equal to the lateral width of a single gate structure overlying the fin.
In a similar vein, in conjunction with a replacement metal gate (RMG) or “gate last” process for fabricating FinFET devices, prior to depositing the gate dielectric and gate conductor layers, a sacrificial gate may be cut to form an opening that is backfilled with an etch selective isolation dielectric layer. Typically, the gate cut is located within an isolation region of the substrate, i.e., over shallow trench isolation, adjacent to one or more active device regions. In an example RMG process, remaining portions of the sacrificial gate are then removed selectively with respect to the backfilled isolation dielectric layer and the resulting cavities filled with a functional gate architecture that is separated from adjacent devices by the isolation dielectric.
In both the single diffusion break and gate cut architectures, a backfilled dielectric layer prevents unwanted current flow between neighboring active regions. As will be appreciated, however, the formation of these and other isolation structures, particularly at advanced nodes, may pose design and processing challenges.